Simultaneously supports up to four posted write transactions, four no posted transactions, and four completion transactions pending in each direction at any time. Each posted write data queue and completion data queue can store up to 8K bytes of data. The no posted data queues can store up to 128 bytes of data. The PCIe interface supports a X1 link operating at full 250 MB it/s packet throughput in each direction simultaneously. Also, the bridge supports the advanced error Reporting capability including ECRC as defined in the PCI Express base specification, revision 1.1. Supplemental firmware or software is required to fully utilize both of these features. Learn More
PCIe x1 Interface Version 1.0, 4-Port Internal SATA 6Gbps Controller Card, Non-Raid, Marvell 88SE9215 Chipset, with Low Profile Bracket. IOCREST newest card with advance Marvell 88SE9215 Chipset single chip 4-port Gen III 6Gb/s host controller. Learn More
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